1. Field of the Invention
This invention relates to a data communication system for performing transmission and reception of data between a plurality of control systems, e.g. electronic control units (hereinafter referred to as "the ECU's"), central processing units (hereinafter referred to as "the CPU's"), etc.
2. Description of the Related Art
Conventionally, as a data communication system between control systems, such as CPU's and ECU's, there have been used an asynchronous serial communication system and a clock-synchronous serial communication system, for instance.
In the asynchronous serial communication system, as shown in FIG. 1, there are provided, between two CPU's 101 and 102, a signal line 103 for transmitting data from an output terminal T1 of the CPU 101 to an input terminal R2 of the CPU 102, and a signal line 104 for transmitting data from an output terminal T2 of the CPU 102 to an input terminal R1 of the CPU 101. In this system, data are transmitted in a data format as shown in FIG. 2. That is, one data frame consists of character bits D0 to D7 and a parity bit arranged between a start bit and a stop bit which are used as reference bits for transmission and reception of data.
On the other hand, in the clock synchronous serial communication system, as shown in FIG. 3, there are provided a clock signal line 113 for transmitting a clock signal between a clock signal terminal SCK11 of a CPU 111, and a clock signal terminal SCK12 of a CPU 112, a data signal line 114 for transmitting data from an output terminal SO1 of the CPU 111 to an input terminal SI2 of the CPU 112, and a data signal line 115 for transmitting data from an output terminal S02 of the CPU 2 to an input terminal SI1 of the CPU 111. In this system, as shown in FIG. 4, a signal 1 and a signal 2 are transmitted and received via the signal line 114 and the signal line 115, respectively, in synchronism with the clock signal transmitted via the clock signal line 113.
The former of the prior art systems, i.e., the conventional asynchronous serial communication system, has a simplified construction since data are transmitted between the two CPU's 101 and 102 via the two signal lines 103, 104, alone. However, since data and clock signals (i.e. the start bit and the stop bit) are sent and received via the same line, the communication speed is low, and further deformed or false data can occur when reference clock pulses used in the respective CPU's 101 and 102 are deviated from proper timing.
On the other hand, the latter of the prior art systems, i.e., the conventional clock synchronous serial communication system, hardly suffers from the problem of occurrence of deformed or false data due to deviated timing of reference clock signals, since the two CPU's 111 and 112 are operated based on common clock pulses, and at the same time enjoys a high communication speed. However, a noise in the clock signal line 113 can be erroneously recognized as the clock signal, whereupon data transmission is started, even when data communication should not be performed.